The present invention relates generally to system-on-a-chip (SOC) applications and more particularly to on-chip buses used in such SOC applications.
Recent advances in silicon densities allow for the integration of numerous functions onto a single silicon chip. With this increased density, peripheral devices formerly attached to a processor at the card level are integrated onto the same die as the processor. As a result, chip designers must address issues traditionally handled by system designers. This type of implementation of a complex circuit on a single die is referred to as a system-on-a-chip (SOC).
Typically, an SOC contains numerous functional blocks representing a large number of logic gates. Design of such a system is realized through a macro-based approach. Macro-based design facilitates logic entry and verification, as well as re-use of macros with particular functionality. A macro is a re-usable tested design available in a library in the form of a netlist. In applications ranging from generic serial ports to complex memory controllers and processor cores, each SOC uses a number of common macros. A core is a re-usable tested design in any hardware description language like VHDL or Verilog.
Many single-chip solutions used in such applications are designed as custom chips, each with its own internal architecture. Logical units within such a chip are often difficult to extract and re-use in different applications. As a result, the same function is re-designed many times from one application to another.
Thus, a need clearly exists for an improved architecture for an on-chip bus used in such SOC implementations that is flexible and robust to support a wide variety of embedded system requirements.
In accordance with a first aspect of the invention, there is provided an apparatus for mastering a Processor Local Bus (PLB) having read and write data buses. The apparatus includes a first module for generating an address phase for read data coupled to the PLB and a second module for generating an address phase for write data coupled to the PLB. The second address phase generating module is adapted to carry out a write operation when the write data bus is idle and the read data bus is busy, and vice versa. Preferably, the first and second address phase generating module are adapted to simultaneously process read and write requests. The apparatus may also include a module for handling read data coupled to the first address phase generating module and a module for handling write data coupled to the second address phase generating module. Still more preferably, the apparatus includes a module for requesting read data coupled to the read-data handling module and a module for requesting write data coupled to the write-data handling module.
In accordance with a second aspect of the invention, there is provided a system on a chip. The system includes:
a processor local bus (PLB);
an arbiter coupled to the PLB; and
at least two masters coupled to the PLB, a first master of the at least two masters including: a first module for generating a first address phase for read data coupled to the PLB; and a second module for generating a second address phase for write data coupled to the PLB. The second address phase generating module is adapted to carry out a write operation when the write data bus is idle and the read data bus is busy, and vice versa.
In accordance with a third aspect of the invention, there is provided a method for mastering a Processor Local Bus (PLB) having read and write data buses. The method includes the steps of: generating a first address phase for read data coupled to the PLB; and generating a second address phase for write data coupled to the PLB. The second address phase generating step is able to carry out a write operation when the write data bus is idle and the read data bus is busy, and vice versa.
In accordance with a fourth aspect of the invention, there is provided a method for providing a system on a chip. The system has a processor local bus (PLB), an arbiter coupled to the PLB, and at least two masters coupled to the PLB. The method includes the steps of: generating a first address phase for read data provided via the PLB; and generating a second address phase for write data provided via the PLB. The second address phase generating step is able to carry out a write operation when the write data bus is idle and the read data bus is busy, and vice versa.
In accordance with a fifth aspect of the invention, there is provided a computer program product having a computer readable medium having a computer program recorded therein for mastering a Processor Local Bus (PLB) having read and write data buses. The computer program product includes: a computer program code module for generating a first address phase for read data via the PLB; and a computer program code module for generating a second address phase for write data via the PLB. The second address phase generation is capable of carrying out a write operation when the write data bus is idle and the read data bus is busy, and vice versa.
In accordance with a sixth aspect of the invention, there is provided a computer program product having a computer readable medium having a computer program recorded therein for providing a system on a chip, the computer program product including:
a computer program code module for providing a processor local bus (PLB);
a computer program code module for providing an arbiter coupled to the PLB; and
a computer program code module for providing at least two masters coupled to the PLB, a first master of the at least two masters including:
first means for generating a first address phase for read data coupled to the PLB;
second means for generating a second address phase for write data coupled to the PLB, the second address phase generating means adapted to carry out a write operation when the write data bus is idle and the read data bus is busy, and vice versa.